The present invention relates to a reverse current stopping circuit of a synchronous rectification type DC-DC converter, which detects a reverse current of an inductor current of an inductor located in an output portion of the synchronous rectification type DC-DC converter and stops the reverse current.
FIG. 7 is a diagram showing the configuration of a reverse current stopping circuit of a synchronous rectification type DC-DC converter according to a conventional art. The synchronous rectification type DC-DC converter uses a synchronous rectification MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Mn in place of a freewheeling diode (not shown) so as to reduce conduction loss, thereby improving efficiency under heavy load conditions. However, the MOSFET used as a synchronous rectification device allows a current to flow therein in a reverse direction. Therefore, when a current is conducted to a switching device Mp (30) and the synchronous rectification MOSFET Mn (hereinafter referred to as “Mn” simply) (110) complementary thereto, an inductor current IL of an inductor L (40) flows back under light load conditions so that the efficiency deteriorates. The inductor L (40) together with an output capacitor Cout (50) forms an output portion of the synchronous rectification type DC-DC converter to supply electric power to a load (not shown). A circuit (reverse current stopping circuit) is used to prevent the inductor current IL from flowing back. The reverse current stopping circuit uses a comparator (720) to detect that a drain to source voltage Vds of the Mn (110) has exceeded 0 V, and turns off the Mn (110).
For example, such reverse current stopping circuits are also disclosed in Japanese Unexamined Patent Application Publications No. JP-A-2006-14482 (paragraphs [0067]-[0072] and FIG. 4: Patent Document 1), JP-A-2006-60977 (Patent Document 2), and JP-A-2007-236194 (Patent Document 3).
In the background-art reverse current stopping circuit of the synchronous rectification type DC-DC converter shown in FIG. 7, the switching device Mp (30) including a P-channel MOSFET and the Mn (110) including an N-channel MOSFET operating complementarily to the switching device Mp (30) are connected in series between an input voltage terminal Vin (2) and the ground, while a series circuit of the inductor L (40) and the output capacitor Cout (50) is connected in parallel to the Mn (110). An end-to-end voltage of the output capacitor Cout (50) obtained from a node between the inductor L (40) and the output capacitor Cout (50), that is, an output voltage Vout (8) is fed back and applied to a controller (10). The controller (10) controls the operation of switching devices provided in the DC-DC converter to obtain a constant output voltage at an output terminal thereof. The controller (10) outputs a first control signal (12) and a second control signal (14) based on the fed-back output voltage Vout (8). The first control signal (12) is supplied to a driver (20). The driver (20) applies a driver output Vgp (25) to a gate of the switching device Mp (30).
On the other hand, the second control signal (14) is supplied to one of input terminals of an AND circuit (60) and a set terminal of a flip-flop (730). The first control signal (12) and the second control signal (14) outputted from the controller (10) are outputted as pulse signals whose duty ratios vary in accordance with the output voltage Vout (8). The duty ratios are in the same phase except for a dead time period provided for preventing the Mp (30) and the Mn (110) from being turned on concurrently (the pulse signals serve to turn off both the Mp (30) and the Mn (110) in the dead time period). A Q output (735) of the flip-flop (730) is applied to the other input terminal of the AND circuit (60). The output of the AND circuit (60) is applied to a driver (70). The driver (70) applies a driver output Vgn (75) to a gate of the Mn (110). A reference voltage (ground potential) is applied to a non-inverting input terminal of a comparator (720).
On the other hand, a potential Vsw (switching terminal voltage) of a node (4) between a drain of the Mn (110) and the inductor L (40) is applied to an inverting input terminal of the comparator (720) through a node (6). An output terminal of the comparator (720) is connected to a reset terminal of the flip-flop (730). Thus, a reverse current stopping circuit (700) includes the comparator (720), the flip-flop (730) and the Mn (110). The set input and the reset input of the flip-flop (730) are negative logic inputs.
The operation of the conventional-type reverse current stopping circuit of the synchronous rectification type DC-DC converter configured as shown above will be explained. The comparator (720) compares the reference voltage (ground potential) with the potential Vsw of the node (4) between the drain of the Mn (110) and the inductor L (40) obtained through the node (6). Upon detection of the fact that the potential Vsw is higher than the reference voltage (that is, a current of the Mn (110) is flowing from the node (4) toward the ground), the comparator (720) outputs a logic L level as an output signal (725), and supplies the logic L level to the reset terminal of the flip-flop (730). Upon detection of the logic L level supplied to the reset terminal, the flip-flop (730) sets the Q output (735) at the logic L level. In response thereto, the AND circuit (60) sets its output (65) at the logic L level. As a result, the driver (70) sets the gate of the Mn (110) at the logic L level so that the Mn (110) cannot be switched on. Thus, the inductor current IL flowing into the inductor L (40) can be prevented from flowing back.
The flip-flop (730) reset in a cycle is set by a trailing edge of the second control signal (14) in a subsequent cycle. As a result, the Q output (735) of the flip-flop (730) has a logic H level to allow the second control signal (14) of the controller (10) to pass through the AND circuit (60) till the logic L level of the output signal (725) is supplied to the reset terminal of the flip-flop (730). The logic H level signal of the second control signal (14) is applied to the gate of the Mn (110) through the driver (70) to switch on the Mn (110). Thus, the reverse current stopping circuit 700 is allowed to operate again.
When the conventional-type comparator in the reverse current stopping circuit of the synchronous rectification type DC-DC converter shown in FIG. 7 is manufactured, some variation in input voltage offset occurs (about ±10 mV in case of CMOS (Complementary MOS)). Due to the variation, the accuracy in detection of a reverse current deteriorates. Particularly in a high-current DC-DC converter, even a very small detection error of a drain-to-source voltage Vds becomes a large current error due to a low ON resistance of the synchronous rectification MOSFET Mn. Thus, it is unlikely that a reverse current can be stopped. It is, therefore, necessary to deal with the variation in input voltage offset sufficiently.
According to Patent Document 1, an offset is provided for detection of an emission current so that the timing when a synchronous rectification MOSFET turned on to emit electric power to a load is turned off can be synchronized with the timing when the emission current is inverted to send back load-side excess electric power. Turning off the synchronous transistor is delayed by the addition of the offset so that the electric power supplied excessively to the load under light load conditions can be sent back. However, there is no suggestion about how to increase or decrease an offset voltage to avoid influence of the variation in input offset voltage of the comparator so as to adjust the threshold level of the comparator to a point where no reverse current exists.
According to Patent Document 2, a reverse current detector circuit having a comparator is provided in a switching power supply unit. In the switching power supply unit, temperature dependency is given to a reference voltage to be supplied to the comparator for detecting a reverse current or an input offset of the comparator, so that a synchronous rectification MOSFET can be turned off at an optimum timing even if the temperature changes. However, there is no suggestion about how to increase or decrease an offset voltage to avoid influence of the variation in input offset voltage of the comparator so as to adjust the threshold level of the comparator to a point where no reverse current exists.
According to Patent Document 3, a circuit independent of a control circuit system of a synchronous rectification MOSFET is used to block a reverse current flowing into the synchronous rectification MOSFET. Thus, it is possible to shorten a delay time between the time when the occurrence of the reverse current is detected and the time when the reverse current is blocked. However, there is no suggestion about how to increase or decrease an offset voltage to avoid influence of the variation in input offset voltage of a comparator so as to adjust the threshold level of the comparator to a point where no reverse current exists.
When a comparator is manufactured by using semiconductor technology, some degree of variation unavoidably occurs in input voltage offset. Thus, accuracy in detection of a reverse current by the comparator deteriorates. In any aforementioned conventional type technique, there is no suggestion about how to increase or decrease an offset voltage to avoid influence of the variation in input offset voltage of the comparator so as to adjust the threshold level of the comparator to a point where no reverse current exists.
Therefore, an object of the present invention is to provide a reverse current stopping circuit of a synchronous rectification type DC-DC converter free from influence of a variation in input offset voltage of a comparator.
Further objects and advantages of the invention will be apparent from the following description of the invention.